(a) Field of the Invention
The present invention relates to a semiconductor integrated logic circuit, and more particularly it pertains to a monolithic semiconductor integrated circuit of the merged transistor logic (MTL) type.
(b) Description of the Prior Art
A merged transistor logic circuit (MTL), conventionally known, is a monolithic semiconductor circuit comprising: inverter transistors having their input terminals and output terminals connected in logic fashion respectively so as to perform the required logic operations; and a plurality of injector transistors for injecting charge carriers into the inverter transistors (c.f. U.S. Pat. No. 3,736,477 granted to Berger et al). Such an MTL circuit attains a remarkable success in realizing a high density packaging and a low power consumption. However, since both the inverter and the injector transistors of known MTL circuits are formed with bipolar transistors, there remains many problems to be solved with respect to the switching speed, power loss, clocking, and so forth in the conventional MTL circuits.
More detailed description of the conventional MTL circuit will be described hereinbelow by referring to FIGS. 1 and 2.
FIG. 1 shows an example of the conventional MTL circuit which is often called an IIL circuit. Inverter transistors (sometimes called driver transistors) Q.sub.d1, Q.sub.d2 and Q.sub.d3 are formed with npn-type bipolar transistors, each having three collectors (as logic outputs) and a base (as a logic input) respectively connected to predetermined succeeding stages and a preceding stage. Actually, a wired AND logic of collectors respectively of the plurality of inverter transistors in the preceding stages is taken and supplied to the base of the inverter transistor of the following stage. Injector transistors Q.sub.i1, Q.sub.i2, . . . are formed with pnp-type bipolar transistors having collectors C connected to the corresponding bases B of the inverter transistors Q.sub.d2, Q.sub.d3, . . . The injector transistors Q.sub.i1, Q.sub.i2, . . . are pnp-type while the inverter transistors Q.sub.d1, Q.sub.d2, . . . are npn-type as described above. Here, the collector regions of the injector transistors Q.sub.i1, Q.sub.i2, . . . also constitute or are merged to the base regions of the inverter transistors Q.sub.d2, Q.sub.d3, . . . , respectively, and the base regions of the injector transistors Q.sub.i1, Q.sub.i2, . . . also constitute or are merged to the emitter regions of the inverter transistors Q.sub.d2, Q.sub.d3, . . . , respectively. Therefore, the base-collector junction of an injector transistor also serves as the emitter-base junction of an inverter transistor. The injector transistors Q.sub.i1, Q.sub.i2, . . . are connected in the common-base (base-grounded) configuration, so that they work as the constant current sources, or more particularly, as the charge carrier supplies.
For example, when a positive voltage is applied to the injection electrode (emitter electrode) I of the pnp-type injector transistor Q.sub.i1 while the npn-type inverter transistor Q.sub.d1 (of the preceding stage) is turned off, charge carriers (positive holes) are injected from the emitter I to the base B and extracted to the collector C of the pnp-type injector transistor Q.sub.i1 and then poured into the base B of the npn-type inverter transistor Q.sub.d2, thereby to let the base current flow and to turn the inverter transistor Q.sub.d2 on. When the driver transistor Q.sub.d1 is turned on thereafter, the charge carriers injected from the injector transistor Q.sub.i1 are absorbed in the turned-on inverter transistor Q.sub.d1 of the preceding stage and the inverter transistor Q.sub.d2 is now rendered off. Similar operations are accomplished in the successive stages. Clocking of the IIL circuit is performed generally by the application of clock pulses to the injection electrodes I of the injector transistors Q.sub.i1, Q.sub.i2, . . . .
In such conventional IIL circuit, the total switching speed of the circuit depends on the switching speed of the respective inverter transistors Q.sub.d1, Q.sub.d2, . . . and injector transistors Q.sub.i1, Q.sub.i2, . . . and also depends on the carrier injection efficiency of the injector transistors Q.sub.i1, Q.sub.i2, . . . (which is equal to the current amplification factor .alpha. in the base-grounded connection). Namely, the turn-off speed of the inverter transistors Q.sub.d1, Q.sub.d2, . . . is limited by the carrier storage effect thereof, since they are bipolar transistors, while the turn-on speed of the inverter transistors Q.sub.d1, Q.sub.d2, . . . is subjected to the influence of the carrier injection efficiency of the injector transistors Q.sub.i1, Q.sub.i2, . . . . In other words, for improving the turn-on speed of the inverter transistors Q.sub.d1, Q.sub.d2, . . . , the injector transistors should inject (pour) sufficiently many carriers into the base region of the inverter transistors Q.sub.d1, Q.sub.d2, . . . so as to raise the base potential rapidly. The carrier injection efficiency a of the injector transistor of the conventional IIL circuit is low and it further rapidly decreases when the injection current (the emitter current of the injector transistor) I.sub.i exceeds the value of about 100 .mu.A, as is shown in FIG. 9. Therefore, the power loss increases for injecting sufficiently many charge carriers into the inverter transistor. Furthermore, even if sufficient charge carriers can be injected, the resultant charge storing effect in the inverter transistor further decreases the turn-off speed. Yet further, since clocking is achieved by applying clock pulses to the injection electrode I of a low input impedance, a considerably large power is required for clocking.
FIG. 2 shows a partial cross-sectional structure of the conventional IIL having a circuit connection as shown in FIG. 1. In FIG. 2, a semiconductor wafer 10 is formed by growing an n-type semiconductor layer 12 of a relatively high resistivity on an n-type (n.sup.+ -type) semiconductor substrate 11 of a low resistivity. In the n-type semiconductor layer 12, p-type semiconductor regions 13 and 14 of a relatively low resistivity are formed by relying on, for example, the selective diffusion technique. In the p-type semiconductor region 14, n-type (n.sup.+ - type) semiconductor regions 15, 16 and 17 of a further low resistivity are formed by, for example, the selective diffusion technique. Respective electrodes 18, 19, 20, 21, 22 and 23 are formed on the exposed surface of the substrate 11 and the semiconductor regions 13, 14, 15, 16 and 17. An oxide layer 24 passivates the surface of the wafer 10 except for the electrode portions. The semiconductor regions 12, 13 and 14 constitute the base, emitter and collector, respectively, of the pnp-type injector transistor Q.sub.i1, while the semiconductor regions 12, 14 and 15 - 16 - 17 constitute the emitter, base and collectors, respectively, of the npn-type multi-collector inverter transistor Q.sub.d2. Namely, the base region 12 of the injector transistor Q.sub.i1 serves also as the emitter of the inverter transistor Q.sub.d2 and the collector region 14 of the pnp-type injection transistor serves also as the base of the npn-type inverter transistor Q.sub.d2.
As can be easily understood from the above-stated structure, in order to decrease the carrier storage effect of the inverter transistor Q.sub.d2, the thicknesses t.sub.1 and t.sub.2 of the portions of the semiconductor regions 12 and 14 indicated in the figure should be reduced sufficiently. From a practical viewpoint, it is very difficult to satisfy such conditions from the viewpoint of manufacture and will cause relatively large variance in the products. Furthermore, there are also limitations from the aspects of other electric characteristics.
Part of the carriers injected from the emitter 13 of the injector transistor Q.sub.i1 is collected (extracted) by the collector and injected again (or double injected) into the emitter. To increase the ratio of charge carriers collected by the collector 14 to the total of the injected (emitted) carriers, the base width which is indicated by WB in the figure should be decreased to as narrow a width as possible. However, there is a limit, from the viewpoint of manufacture, in decreasing this width of the base WB in the lateral bipolar transistor. This constitutes the main reason for the low carrier injection efficiency .alpha.. Furthermore, as the number of charge carriers collected to the collector 14 will increase while the preceding stage inverter transistor is rendered off, the potential at the collector 14 will increase to cause a reverse or backward injection to develop from the collector to the base. Furthermore, the emitter-base PN junction is forwardly and deeply biased, and hence the effect of the base resistance will become to play a larger role to raise the ratio of carriers travelling to the semiconductur substrate. This is the cause for the above-mentioned phenomenon that the carrier injection efficiency .alpha. decreases as the injection current I.sub.i increases beyond a certain value.